In a manufacturing process of a semiconductor device, there is a CMP (Chemical Mechanical Polishing) technology as a planarization technology of a film surface. In the CMP process, for example, silicon oxide (SiO2) and the like formed on a semiconductor substrate are used as a to-be-processed film and the surface of the film is planarized.
However, in the CMP process, a slurry containing abrasive grains is used. Because of this, after the CMP process, the surface of the to-be-processed film is damaged (scratched) by polishing executed using the abrasive grains.
In contrast, recently, in a semiconductor memory, a novel structure is being introduced together with miniaturization to increase a capacity and to reduce a power consumption. In a generation employing a half pitch of 20 nm or less and a generation thereafter, an air gap is introduced as an insulation layer having a low dielectric constant to secure an insulating property between electrodes (wirings).
When such air gap is formed accompanying with miniaturization, a mechanical strength of a device is greatly lowered. For this reason, when a surface of the to-be-processed film on the air gap is planarized by the CMP technology, an air gap portion is shear damaged (cracked) by a shearing stress at the time of the CMP process in addition to the generation of the scratches.